1. Field of the Invention
This invention relates to a mesa type semiconductor device having a mesa groove and its manufacturing method.
2. Description of the Related Art
A mesa type power diode has been known as one of the mesa type semiconductor devices. A mesa type diode according to a prior art is described referring to FIG. 9.
An N−-type semiconductor layer 102 is formed on a surface of an N+-type semiconductor substrate 101. An insulation film 105 is formed on a P-type semiconductor layer 103 that is formed on a surface of the N−-type semiconductor layer 102. Also, an anode 106 electrically connected with the P-type semiconductor layer 103 is formed.
There is formed a mesa groove 108 that extends from a surface of the P-type semiconductor layer 103 to the N+-type semiconductor substrate 101. The mesa groove 108 penetrates through the N−-type semiconductor layer 102 and its bottom is located inside the N+-type semiconductor substrate 101. Sidewalls of the mesa groove 108 are tapered down to the bottom of the mesa groove 108 to have a normal tapered shape. The mesa type diode is surrounded by the mesa groove 108 to have a mesa type structure.
A passivation film 130 is formed to cover the sidewalls of the mesa groove 108, and a cathode 107 is formed on a back surface of the semiconductor substrate 101.
The mesa type semiconductor device is described in Japanese Patent Application Publication No. 2003-347306, for example.
However, experiments conducted by the inventors showed that the mesa type diode according to the prior art did not have a high enough withstand voltage when it was reverse biased. It is considered that the withstand voltage is reduced by an electric field convergence at a PN junction JC under the reverse bias, which is caused because the sidewalls of the mesa groove 108 around the PN junction JC have the normal tapered shape.
The inventors have found that the withstand voltage could be improved by forming the sidewalls of the mesa groove 108 vertical to the surface of the semiconductor substrate 101. It is conceivable that a Bosch process, which is a dry etch process capable of forming a high aspect ratio structure, is used to form the vertical sidewalls of the mesa groove 108.
When the Bosch process is used, however, a damaged layer is formed in the sidewall of the mesa groove 108. The damaged layer causes a leakage current when the reverse bias is applied to the mesa type diode. The damaged layer can be removed by wet etching. However, the wet etching transforms the sidewalls of the mesa groove 108 around the PN junction JC into the normal tapered shape as in the prior art shown in FIG. 9, and the withstand voltage is reduced.